Samsung Electronics recently announced plans to launch its advanced 3D chip packaging technology called SAINT (Samsung Advanced Interconnect Technology) in 2024. The core of this technology is to enable efficient memory-processor integration for high-performance chips such as AI chips through more compact package sizes.SAINT technology is expected to be available in three different packaging solutions: SAINT S (vertical stack for SRAM and CPU), SAINT D (vertical package for processors such as CPUs and GPUs with DRAM memory), and SAINT L (stacking scheme for application processors).
Samsung has now successfully completed validation testing of the SAINT technology and plans to work with customers on further testing. The company expects to expand its services later next year, with the main goal of improving the performance of data center AI chips and smartphone application processors with AI capabilities.
In the semiconductor industry, advanced packaging technologies for 3D chips are gaining traction as component miniaturization processes are approaching their physical limits. In addition to Samsung, major foundries such as TSMC, Intel and UMC are actively developing their own 3D chip packaging technologies. Among them, TSMC is testing and upgrading its 3D inter-chip stacking technology SoIC on a large scale to meet the needs of customers including Apple and NVIDIA; Intel has adopted its next-generation Fooveros 3D chip packaging technology for the production of advanced chips; and UMC has recently launched a wafer-to-wafer (W2W) 3D IC project, which utilizes silicon-on-stacking technology to provide memory and processors using silicon stacking technology to provide cutting-edge solutions for the efficient integration of memory and processors.
