As the global semiconductor industry continues to tilt towards high-performance computing (HPC) and artificial intelligence (AI) scenarios, HBM (high-bandwidth memory), as a key device to break through the bottleneck of data transmission, is becoming the focus of storage technology evolution. As a long-term leader in the global DRAM market, Samsung Electronics has once again put it in the spotlight of the industry due to its delimma status quo in the development of HBM4 chips.
On the one hand, Samsung has made significant progress in HBM4 logic chips: the test yield of logic dies manufactured using the 4nm process has reached 40%, which is much higher than the general starting level of 10% for new nodes in the industry. On the other hand, the planned 1c nm DRAM chip is limited by the problem of capacitance leakage, and the development progress is delayed, which seriously restricts the commercialization pace of the HBM4 overall solution. This situation of one joy and one worry reflects the challenge of interweaving multiple complex variables of "manufacturing process-material physics-system packaging" in the research and development of high-end memory chips, and also adds many variables to Samsung's future position in the high-performance storage market.
Ⅰ. The competitive landscape of the HBM market: from "failure" to "counteroffensive".
High-bandwidth memory has become the standard for AI servers and GPU accelerators. According to TrendForce's data in early 2024, the global HBM market has entered a period of rapid growth, and HBM3/3E shipments are expected to increase by more than 200% year-on-year in 2024. SK hynix, with its technological maturity and reliable supply capabilities in HBM3 and HBM3E, once accounted for more than 70% of HBM shipments in 2023, becoming the HBM market leader, while Samsung's market share fell sharply.
The reasons for this are that Samsung's problems in the HBM3 stage are mainly focused on the following points:
- Insufficient yield: HBM products mostly use 2.5D/3D packages with stacked DRAM + logic die, which has extremely high requirements for package yield and thermal management. Samsung's yield control in TSV (through-silicon via) consistency and die stacking is not as good as SK hynix;
- Long product validation cycle: Joint development and testing with large GPU customers (such as NVIDIA and AMD) are not effectively synchronized, resulting in a missed commercialization window.
- Differences in packaging strategies: SK uses mature hybrid bonding and cold-pressing technologies, while Samsung's early TC-NCF (hot-pressed non-conductive) solution faced greater heat dissipation and warpage control challenges when stacking more than 12 layers of DRAM dies.
Ⅱ. HBM4 logic chip: Samsung's key breakthrough point
Currently, the HBM market is accelerating its evolution to the next-generation HBM4. Compared with HBM3E, HBM4 not only has a significant increase in bandwidth (more than 1.2TB/s per stack), but also introduces more advanced packaging architecture and power management mechanisms. The importance of HBM4 logic dies has never been greater, as it not only controls the DRAM stack and interfaces, but also directly affects the power consumption and stability of the entire memory system.
According to a March 2024 report by BusinessKorea, Samsung's HBM4 logic chip uses its own 4nm EUV process and achieves a yield rate of 40% in the early testing stage, which is not easy in advanced process chips. This is not only significantly higher than the industry average starting yield (typically 10%-20%), but also reflects Samsung's system capabilities in FinFET process optimization, power integrity design, and back-end packaging synergy.
The early success of Logic Die won Samsung confidence in the market. According to industry sources, Samsung has shown its HBM4 samples to customers including Nvidia, Intel and AMD, and some customers have already started the verification phase. This move undoubtedly laid the technical foundation for Samsung to compete for the dominance of the HBM4 market.
Figure: Samsung's HBM4 logic chip has a 40nm process yield of 40%, making significant progress
Ⅲ. The 1c nm DRAM dilemma: leakage bottleneck and mass production risk
Despite the good news about logic chips, the DRAM part of Samsung's HBM4 solution has encountered tricky problems. The HBM4 standard typically consists of 12 layers of stacked DRAM dies, and the data integrity and energy efficiency performance of each layer of chips are directly related to the yield and reliability of the overall product.
Samsung plans to adopt its latest 1c nm DRAM process node, but according to Korean media "ETNews" and a number of analysts, the capacitor leakage problem has become a key obstacle to its advancement. Since the 1z nm node, as the capacitor size limit shrinks and the oxide thickness is insufficient, the charge retention capability in DRAM decreases, resulting in an increase in the refresh rate required to maintain the data state, which significantly affects chip power consumption and stability.
Samsung tried to improve the reliability of the capacitor structure by "appropriately relaxing the linewidth" (with a slight setback relative to the 1a nm node), but it still failed to meet the stringent standards required by HBM. In addition, the original plan to start mass production in the second half of 2024 is expected to be delayed by at least six months, as 1c nm DRAM has not yet completed commercial validation.
This delay may not only affect Samsung's overall HBM4 product launch cadence, but also increase the likelihood that GPU customers will switch to SK hynix or Micron as the HBM4 is upgraded from generation to generation.
Ⅳ. The hidden concerns and differentiation challenges of packaging technology
HBM's products are the ultimate challenge to advanced packaging technology. One of the main differences between Samsung and SK hynix is in the packaging solution. Samsung uses the "TC-NCF" (Thermal Compression - Non-Conductive Film) hot-pressed packaging method, which has the advantage of compact structure and good dielectric properties, but the disadvantages are:
- The temperature control accuracy is extremely high during hot pressing, and it is easy to warp;
- When stacking at a high level (e.g., 12Hi), the heat dissipation path is complex, which is prone to local hot spots.
- It is difficult to solve the problem of matching the coefficient of thermal expansion between the substrate and the substrate, which leads to the failure of package stress after long-term operation.
SK hynix's cold-pressed bonding and hybrid bonding methods are more suitable for its high-level DRAM die stacking strategy, and the market feedback has been stable. This is one of the important reasons why the HBM3E generation SK was the first to achieve mass production.
If Samsung fails to make a breakthrough in DRAM yield and package thermal control management, even if the logic die performs well, the overall HBM4 product may still face multiple headwinds such as unstable performance, rising costs, and customer hesitation.
Ⅴ. Strategic outlook and countermeasures
At this stage, Samsung's challenges are more reflected in the ability to break through systemic bottlenecks rather than single-point technical shortcomings. In view of the future mass production and commercial promotion of HBM4, it is recommended that Samsung accelerate the improvement in the following directions:
1. DRAM process optimization: It is necessary to strengthen the research on capacitive materials at the 1c nm node, and consider introducing new high-k materials or three-dimensional capacitor structures to improve charge retention.
2. Multi-process parallel strategy: Before 1C is stabilized, a more mature 1A or 1B node can be temporarily used to deal with initial market orders to avoid missing the commercial window again.
3. Package solution improvement: further optimize the hot-pressing packaging process or evaluate the introduction of hybrid bonding technology to improve thermal control and stacking reliability;
4. Ecological linkage cooperation: Establish a closer linkage cooperation mechanism with GPU and server chip customers, and intervene in product definition and packaging standard formulation in advance;
5. Rhythm control of investment and expansion plan: Avoid blindly expanding the investment in HBM4 production line when DRAM is not yet mature, and reduce the risk of resource misallocation.
Concluison
HBM has become a barometer to measure the technical strength of a memory chip manufacturer. Samsung Electronics' breakthrough in HBM4 logic chips is gratifying, but the DRAM process challenges and packaging challenges it faces cannot be ignored.
The current situation of "ice and fire" reminds us that in the fierce competition of high-end semiconductors, the success of a single link is not enough to support the overall leadership of system-level products. In the future, whether Samsung can reshape the dominance of the HBM market depends not only on the technical extension of its logic chips, but also on its continuous evolution in system engineering integration and upstream and downstream collaboration.
Driven by AI acceleration and growing demand for HPC, HBM4 is likely to be a key battleground for Samsung's next round of counteroffensive. But the premise is that Samsung must first pass through this fog of "capacitance leakage".
