Reporter: Ana Hu
China exportsemi net
According to China exportsemi net, at the recently held IEDM 2023 (2023 IEEE International Electronic Devices Conference), Intel's new breakthrough in back-side power supply technology was demonstrated, which uses back-side power contacts to reduce the size of transistors to 1 nanometer, or even More key technologies. Intel says they will have 1 trillion transistors integrated into a single package by 2030. This also heralds the advent of the angstrom era of process technology (1 angstrom is equal to one ten billionth of a meter, which is one-tenth of a nanometer).
Figure 1: Intel’s key technology for shrinking transistors into the 1nm range and beyond using backside power contacts
Intel said that they will continue to advance Moore's Law research, including 3D stacked CMOS transistors with backside power supply and direct backside contacts, expansion paths for backside power supply R&D breakthroughs (such as backside contacts), and 300 CMOS transistors on the same block. Large-scale monolithic 3D integration of silicon transistors and gallium nitride (GaN) transistors on millimeter wafers rather than packages.
With the continuous development of Moore's Law, semiconductor process technology is getting higher and higher, and chip integration is also increasing. "We are entering the angstrom era of process technology. Looking forward to the future of the 'Five Process Nodes in Four Years' plan, continuous innovation ratios "It has never been more important," said Sanjay Natarajan, senior vice president and general manager of component research at Intel Corporation. Cutting-edge technology for energy-efficient power supply. "
According to IDC, the global artificial intelligence hardware market (server) will grow from US$19.5 billion in 2022 to US$34.7 billion in 2026, with a five-year compound growth rate of 17.3%. Among them, the market size of servers used to run generative artificial intelligence servers will account for 31.7% of the overall artificial intelligence server market from 11.9% in 2023 to 2026.
Intel also revealed that PowerVia back-side power supply technology, glass substrates for advanced packaging and Foveros Direct technology are expected to be put into production before 2030. PowerVia back-side power supply technology is expected to be launched with the Intel 20A process node in 2024.
"Moore's Law drives further integration of transistors, which in turn drives more layers and smaller wires, increasing complexity and cost. Each layer must provide signal and power wires, which often results in optimization compromises And the competition for resources creates interconnect bottlenecks, and things are becoming more and more challenging," said Mauro Kobrinsky, Intel's director of technology development. "Backside power fundamentally changes this situation. Using power vias on both sides of the device and in vertical interconnects we will be able to deploy this technology in Semiconductor Intel 20A (2nm) and 18A (1.8nm) next year, which means fewer wires on the front, so we can relax. spacing, optimization compromises are no longer necessary. ”
“In addition to power vias, our research also involves backside contacts, and for the first time we have been able to make these contacts on both sides of the device, both front and back. The contacts eliminate the need for wiring using power vias. This allows us to reduce the capacitance of the battery, improve performance and reduce power consumption,” Kobrinski added.
Intel believes transistor scaling and backside powering are key to meeting the world's exponential growth in demand for more powerful computing power. With the improvement of backside power supply technology and the adoption of new 2D channel materials, Intel is committed to continuing to advance Moore's Law and achieving the integration of 1 trillion transistors in a single package by 2030.
Source: The Paper
