Advanced integrated circuit packaging has become a new focus of competition among AI processors and other high-end integrated circuit (IC) manufacturers, as well as an important frontier for the United States government to reduce its dependence on foreign suppliers and curb Chinese technology development.
However, unlike the severe restrictions imposed by the United States on the "front-end" of China's IC wafer manufacturing through sanctions, China has a strong market share and advanced technology in the "back-end" assembly, packaging and test (APT) of integrated circuits, so it is relatively unaffected by the United States technology blockade in this regard.
TSMC, the world's largest integrated circuit foundry, is rapidly expanding its chip-on-wafer (CoWoS) packaging capacity. The move will alleviate the supply bottlenecks faced by Nvidia, AMD and Intel as they manufacture the latest AI processors at sub-5nm process nodes.
Huawei's progress on sub-5nm processes has been limited by the United States' ban on the sale of ASML's EUV lithography machines to China. However, Huawei's IC design and packaging technology has successfully broken through the United States Department of Commerce's performance limits on the Nvidia chips it sells in the United States.
Specifically, there are reports that Huawei's new Ascend 910C processor outperforms Nvidia's simplified H20 and could be commercially shipped in the next two months.
In the current global technology competition, advanced IC packaging technology has become the next important battlefield of the chip war. As the iteration speed of Moore's Law slows down, the physical limit of chips is gradually approaching, and advanced packaging technology has become a critical path to improve system performance. It allows engineers to put multiple chips into a single package without having to shrink the chip itself, achieving the goal of exceeding the performance of a single chip.
Figure: Advanced IC packaging may become the next battlefield of the chip war
Advanced packaging technologies mainly include 2.5D and 3D packaging. 2.5D packages enable interconnect between chips by stacking or placing die side by side on top of an interposer through through-silicon via (TSV) technology. 3D packaging, on the other hand, further stacks logic or storage dies vertically, connected by an active interposer, for higher integration and shorter interconnect lengths. TSV technology is key in 3D IC packaging, enabling the electrical connection between chips through vertical interconnects.
In addition, wafer-level packaging (WLP) and integrated fan-out (InFO) technology developed by TSMC are also important advances in the field of advanced packaging. WLP enables the shortest electrical path in flip chip form, increasing speed and reducing parasitic effects while reducing costs. InFO technology provides room for integration of multiple chips and is suitable for packaging RF, wireless, processor, baseband, GPU and network chips.
With the development of technology, advanced packaging is developing in the direction of miniaturization, multi-pin, and high integration to meet the needs of mobile devices, high-performance computing and other fields. China is also developing rapidly in this field, and domestic packaging and testing factories such as Changdian Technology are striving to catch up with the international advanced level, and are expected to lead the development of the industry in the accelerated stage of domestic substitution.
However, the chip wars are not limited to technology. Geopolitical power struggles also affect the pattern of the chip industry. United States' tightening of chip export controls on Chinese mainland and China's cultivation of local industrial chains reflect the strategic position of chips in the global economy and military power. The outcome of this war will profoundly affect the global economic structure and the direction of scientific and technological development.
