Artificial intelligence (AI) has become a key driving force for innovation and development in the field of panel-level packaging, including optimizing design, improving production efficiency and quality, and accelerating the R&D process. On the panel-level packaging production line, computer vision technology and AI algorithms are used to monitor all aspects of the production process in real time. AI can quickly identify small defects in die attach processes, wire bonding, and more with far more accuracy than manual inspection. Once a problem is found, the system can send out an alarm in time and give adjustment suggestions, effectively reducing the defective rate. AI can also dynamically optimize the parameters of production equipment based on real-time production data, realize automatic adjustment of production processes, reduce equipment idle time, and greatly improve production efficiency. Panel-level packaging (PLP) is an innovative approach that is gradually replacing traditional round wafer packaging technology with the aim of improving production efficiency and yield.
TSMC recently unveiled a roadmap for 9x reticle-size packaging to meet the demand for large-scale system-in-package. A multi-mask package is one that contains a chip with an area of more than 800 square millimeters in one package. Currently, Nvidia's Blackwell package contains two chips slightly larger than 800 square millimeters, as well as eight layers of high-bandwidth memory (HBM) stacking, each offering 193 GB of memory. It is expected that this year (2025), TSMC will introduce a super carrier board interposer with 6 times the mask size to improve the manufacturing process and yield of the multi-mask packaging process. TSMC reports that the size of the interposer could reach 5,148 square millimeters.
The traditional COWoS-L process still uses a round substrate for packaging, which means that approximately 64 dies can fit on each substrate. However, round substrates limit throughput and can cause yield issues. To this end, the industry has been working on square substrates to increase throughput and improve yields, as square substrates can accommodate more square dies than round substrates. Since 2016, Fraunhofer IZM has been working with 17 international partners on square substrates or panel-level packaging (PLP).
Figure: Artificial intelligence drives semiconductor packaging technology: panel-level packaging is emerging (Source: 3DInCites)
Currently, companies such as TSMC and Intel are also developing processes and technologies to achieve large-format substrates of 600 mm × 600 mm.
ASE Semiconductor, an industry-leading packaging and testing services company, announced on February 22 that it plans to build a panel-level packaging pilot line in Kaohsiung, Taiwan, to install experimental equipment that can handle 600mm × 600mm substrates instead of traditional 300mm round wafers. TSMC expects production of multi-mask packages to increase from approximately 35,000 units in 2024 to 75,000 units in 2025 and 135,000 units in 2026. The opening of a PLP facility by ASE is not only beneficial to TSMC, but also provides an opportunity for chip companies with ASE as a packaging partner for panel-level packaging.
However, one of the challenges in the transition to PLP and future glass substrates is the lack of equipment to support 600mm × 600mm panels. ASE said it will invest up to $200 million to develop PLP equipment. However, thanks to the work of Atotech and Evatec in Fraunhofer's PLP 2.0 Alliance, as well as the efforts of companies such as Onto Innovation's recent PLP Lab, ACM Research, YES and others, there are already multiple tools available for evaluation and potentially ready for mainstream production. In addition, the introduction of flux cleaning, panel cleaning, chamfer etching, metal deposition, inspection, and lithography equipment is also driving the development of PLP technology. Several chemical companies are also involved in the development of critical chemicals.
Advances in artificial intelligence are driving innovation in semiconductor packaging technology, and panel-level packaging is gaining traction and adoption as an effective way to improve production efficiency and yield.
