With the rapid development of electronic technology, the design of SoCs is facing unprecedented challenges, and the integration of AI technology has brought a new dawn to it. On the EDN website, there is an article on How AI is changing the game for high - performance SoC designs, which delves into the changes that artificial intelligence is driving in the field of high-performance system-on-chip (SoC) design. The website focuses on the field of integrated circuit design, focusing on providing professional knowledge sharing and industry insights for IC designers, and has a high degree of professionalism and authority in the fields of semiconductor and integrated circuit design. Here's a breakdown of the core content of the article:
Today, SoCs are growing exponentially in size, complexity, and customization. From the perspective of application scenarios, automotive autonomous driving systems need to process a large amount of sensor data in real time, which has strict requirements for low latency and high reliability. IoT devices need to take into account both low power consumption and efficient data processing to meet the needs of long-term operation and massive data interaction. In pursuit of a smoother user experience, consumer electronics products have also put forward higher standards for chip performance. These specific application requirements make it difficult to meet the needs of off-the-shelf general-purpose chips, and custom SoCs have become an inevitable trend. Custom SoCs offer significant advantages in miniaturization and integration, such as the stringent chip size and weight requirements for wearables and medical implants, that reduce system complexity, power consumption, and cost, as well as achieve higher performance with advanced process technologies, by integrating multiple functions on a single chip.
However, the complexity of SoC design is increasing by the day. Each IP core has a unique interface width and frequency, and multiple standard interfaces and protocols in the industry, such as AXI, AHB, and APB, coexist. In addition, SoCs often integrate IP from different vendors, with different interface requirements. Traditional network-on-chip (NoC) technologies have played an important role in solving connectivity and data transmission problems, but they have become increasingly inadequate in the face of increasingly complex designs. In the absence of automation, designers often add additional switches, buffers, or pipeline stages to ensure the reliability of their designs. However, this approach can lead to a series of problems, as too many switches will take up a lot of chip area and consume more power consumption; Excessive buffering increases latency and power consumption; If the buffer is too small, it will cause data congestion; Excessive use in the pipeline stage will lead to increased latency and more power and silicon wafer resources. Existing NoC interconnect solutions offer manual optimization tools, such as topology selection and parameter fine-tuning, but they still struggle to keep up with the increasing complexity of modern SoC designs.
Figure: AI is reshaping the high-performance SoC design landscape
To address these challenges, a new breed of smart NoC interconnect IP has emerged, exemplified by Arteris' FlexGen smart NoC IP. Today's high-end SoCs typically have between 50 and 500+ IPs, with 1 million to more than 1 billion transistors per IP, and 1 billion to more than 100 billion transistors in the entire SoC, with 5 to 50+ subsystems, making it nearly impossible to design a NoC without intelligent assistance.
FlexGen Intelligent NoC IP dramatically accelerates the design process and improves design quality for efficient, high-performance SoCs with intelligent heuristics using machine learning (ML) technology. Designers simply enter the SoC's high-level specifications, including the socket specifications of the interface, connectivity requirements, and performance targets, through an intuitive interface. Based on this information, FlexGen's ML algorithm determines the optimal NoC topology for different areas of the SoC, automatically generating an intelligent NoC architecture that includes switch, buffer, and pipeline stages. In doing so, it meets user-defined constraints and performance targets while reducing line lengths and latency, resulting in a system IP that can be used directly for physical synthesis.
Compared to traditional NoC design flows, FlexGen has significant advantages. It delivers expert design results up to 10 times faster, with up to 30% reduction in line length and typically more than 10% latency, while also delivering significant improvements in power, performance, and area (PPA) metrics. This dramatically accelerates the development of NoCs, reduces time-to-market, and increases engineering productivity.
In summary, the application of artificial intelligence in high-performance SoC design, especially the emergence of intelligent NoC IP, provides an effective way to solve the complex problems faced by current SoC designs. With the continuous development and improvement of AI technology, it is expected that more innovative approaches will be created in the field of SoC design in the future, which will continue to improve the performance and market competitiveness of SoCs, and push the entire semiconductor industry to new heights.
