Arteris, Inc., a system IP provider focused on accelerating system-on-chip (SoC) creation, today announced an innovative evolution of its network-on-chip (NoC) IP offerings with the addition of tiling capabilities and expanded grid topology support.
Network on Chip (NoC) is an architecture for internal communication in a system-on-chip (SoC). It enables different processing units and modules to exchange data efficiently by designing multiple interconnected network nodes on the chip. The advantage of NoC is its ability to handle complex communication requirements, increase bandwidth, reduce latency, and support multiple communication protocols and architectures for modern multi-core processors and highly integrated chip designs.
These new capabilities significantly accelerate the development of artificial intelligence (AI) and machine learning (ML) computing in SoC designs, enabling design teams to achieve more than 10x higher compute performance while meeting project schedules and power, performance, and area (PPA) targets.
Tiling of network-on-chips is an emerging trend that leverages robust and proven NoC IP to facilitate scaling, reduce design time, speed up testing, and reduce design risk. By replicating soft tiling across the entire chip, SoC architects are able to create modular, scalable designs, with each soft tile representing an independent unit of function, enabling faster integration, verification, and optimization.
Figure: Arteris accelerates AI chip innovation
Arteris' flagship NoC IP products, FlexNoC and Ncore, combine tiling and mesh topologies to revolutionize the growing amount of AI computing power in SoCs. As AI systems continue to grow in size and complexity, the introduction of soft tiling allows design teams to scale quickly without impacting the design of the entire SoC, a combination that can reduce auxiliary processing unit (XPU) subsystem design time and overall SoC connection execution time by up to 50% compared to manually integrated non-tiled designs.
The first iteration of NoC tiling organizes network interface units (NEUs) into modular, repeatable blocks, significantly improving the scalability, efficiency, and reliability of SoC designs. These designs are capable of supporting increasingly complex AI computing workloads, including visual recognition, machine learning (ML) models, deep learning (DL), natural language processing (NLP), and generative AI (GAI), for training and inference, including edge computing.
Srivi Dhruvanarayan, VP of Hardware Engineering at SiMa.ai, said, "With Arteris' highly scalable and flexible grid-based NoC IP, our SoC team can more efficiently handle larger volumes of AI data and complex algorithms. Working closely with Arteris, we have built an Arm-based, multimodal, software-centric edge AI platform that supports multiple models from CNNs to multimodal generative AI, with performance that scales with demand. We look forward to deploying the expanded Arteris NoC tiling and mesh capabilities to further enhance our ability to create a highly scalable AI silicon platform for the edge."
Arteris President and Chief Executive Officer, K. "Arteris continues to innovate and the revolutionary NoC soft tiling capability based on large mesh topologies marks a significant advancement in SoC design technology," said Charles Janac. Our customers are building advanced AI-driven SoCs that enable them to accelerate the development of larger, more complex AI systems with greater efficiency while meeting project timelines and PPA targets.”
