AI has been a hot topic in the field of semiconductor electronic design automation (EDA) and intellectual property (IP) chip design. However, there are differing opinions in the industry on whether generative AI can play a leading role in chip design and manufacturing. In Will Generative AI Play a Leading Role in Chip Design and Manufacturing? In the article, experts from the EDA IP, systems and standards space, including Dai Lu, Chairman of Accellera Standards, Joe Costello, CEO of Metrics, Manuel Rei, Director of Semiconductor Solutions Experience at Dassault Systèmes, Eric Beyne, Microsoft Spokesperson and Senior Fellow at imec, Mayank Bhatnagar, Director of Product Marketing at Cadence Silicon Solutions Group, and Arif Khan, Group Director of Advanced Product Marketing at Cadence, shared the impact of generative AI and what it takes for chiplets/3D-ICs to succeed in the chip market. The following editor of China's overseas semiconductors will interpret the core content of the article:
The Impact of Generative AI on EDA IP Design and Manufacturing
Bringing new opportunities
LuDai points out that EDA tools that require iterative optimization, such as computationally intensive back-end processes and some front-end simulations, are good suited to AI technology. Processes that could not be completed prior to tape-out due to the amount of computation required in the past are now expected to be reconsidered. In addition, generative AI is a disruptive technology that will provide opportunities for startups to change the competitive landscape of the industry. Moreover, China may have a potential advantage in AI due to its access to datasets that are not subject to typical privacy standards.
Manuel Rei believes that generative AI is revolutionizing EDA IP design and manufacturing. It automates and optimizes complex tasks traditionally done manually, accelerating the design cycle and reducing time-to-market for new semiconductors by automating layout synthesis, circuit design, and optimization. AI-driven design exploration helps uncover innovative architectures and circuit topologies to improve performance metrics such as power efficiency and speed. At the same time, AI models can predict and prevent design errors in advance, improving reliability and reducing costly rework in the manufacturing process. In addition, AI can tailor designs to specific needs without sacrificing performance, optimize supply chain management, and assist in the generation and protection of intellectual property, facilitating collaboration among global design teams.
A Microsoft spokesperson mentioned that AI can dramatically improve the productivity of designers, with Nvidia's two initial aids focused on documentation and defect characterization already delivering about 25 percent efficiency gains. AI can also automate iteration processes to compensate for labor shortages, making it an indispensable assistant for engineers.
The Challenge
Joe Costello is skeptical that generative AI can have a significant impact in EDA IP design in the short term. On the one hand, he argues, generative AI training requires a lot of data, while EDA IP is mostly proprietary, data details are encrypted, and open-source design data is insufficient and the quality needs to be improved, and relying on design data within a single company alone cannot meet the training needs. EDA IP designs, on the other hand, require so much precision that "almost" is not enough, and today's generative AI can produce impressive output in areas such as graphics, but it is still difficult to achieve exactly what is expected, let alone to achieve error-free IP design.
Chiplet / 3D - A necessity for ICs to succeed in the chip market
Standards and ecological construction
LuDai believes that for chiplets to grow, they need a diverse library that can support system-on-chip (SOC) development, as most of the companies interested in chiplets are specialized IP vendors. At the same time, standards-based 3D-IC interface compatibility is required between major foundries. In addition, designers should not blindly rely on chiplets to solve all problems, but should first solve some technical challenges with complexity-based SOC chiplet designs before entering the IP chiplet market.
Mayank Bhatnagar emphasized the importance of establishing standard interface IP to encourage collaboration and innovation in the chiplet ecosystem. The Universal Chiplet Interconnect Express (UCIe) interface is becoming a mainstream choice for chiplet interconnects, and its die-to-die signaling communication standard helps heterogeneous chiplet architectures gain support from mainstream commercial chip manufacturers.
Figure: Can generative AI dominate chip design and manufacturing? (Source: Design News).
Technology and industrial support
Manuel Rei noted that standardization of interconnects and design methodologies is critical to the compatibility and ease of integration of chiplet and 3D-IC designs. Advanced packaging technologies, such as through-silicon vias (TSVs) and effective thermal management, are essential to support high-density interconnects and heat dissipation. Enhanced EDA tools are critical to addressing the complexities of multi-chip integration, along with improved verification and testing methods to ensure reliability. In addition, a strong manufacturing ecosystem, including foundries and outsourced semiconductor assembly and test (OSAT) companies, as well as effective supply chain coordination, are essential to support production. Achieving economies of scale in chiplet production and developing cost-effective packaging solutions will help them compete with traditional designs. A clear IP management and licensing framework, as well as compliance with regulatory standards, are also essential.
A Microsoft spokesperson said that the real 3DIC is still largely experimental and difficult for ASIC/SoC designers to use easily. 2.5D is the next reality, but there are currently limited tools available. 2.5D Heterogeneous Integration (HI) with Active Interposer is a chipset-based alternative that offers many of the benefits of high integration with more managed divide and conquer strategies, but with less EDA support for HI beyond signal integrity analysis. The success of chiplet technology also requires interconnect standards, data security, and die/wafer-level data sharing collaboration solutions for interposer design.
Eric Beyne mentioned that for chiplets to become mainstream, they must be able to fit tightly together in a package to ensure a fast, high-bandwidth electrical connection between them, just like functionality in a monolithic SoC. Depending on the 3D system integration platform used, 2.5D chiplet integration connects chips side-by-side via a common substrate (also known as an interposer) and 3D-SoC stacks chiplets on top of each other, the latter being suitable for high-performance computing applications.
Generative AI presents both great potential and challenges in chip design and manufacturing. Chiplet / 3D - IC If you want to take off in the chip market, you need to work together in many aspects such as standard formulation, technological breakthroughs, and industrial ecological construction. If industry companies can solve these problems in advance, they will have an advantage in improving chip design productivity and innovation, and promote the semiconductor industry to a new stage of development.
