At a time when the semiconductor industry is booming, chiplet technology has become the focus of attention. By splitting a complete system-on-chip (SoC) chip into multiple chiplet modules, this technology opens up new possibilities for improving chip performance and optimizing power efficiency, and the automotive industry and others are also looking forward to providing consumers with more diverse choices. However, as with any emerging technology, chiplets face a number of challenges along the way, with the power supply being a particular issue. An article from SemiEngineering, a professional website focusing on semiconductor engineering, explores a series of power challenges caused by chiplet technology, providing cutting-edge technology information, in-depth analysis reports, and industry trend interpretation for engineers, technicians, and business managers in the semiconductor industry. The following editor of China Exportsemi will give a brief introduction to the original text:
In the field of chip manufacturing, chiplets are gradually emerging. It splits a single system-on-chip (SoC) chip into multiple chiplet modules, which has many benefits, such as improved performance and power efficiency, and the automotive industry wants to use it to provide consumers with more choice. But at the same time, chiplets also bring a new set of power challenges that make chip designs more complex.
In the past, when designing a single SoC chip, although there were also power considerations, all parts were on the same chip, and the problem was relatively easy to understand and solve. Now with small chips, when multiple small chips are combined, the situation becomes much more complicated. Like the development of artificial intelligence, the requirements for computing power are getting higher and higher, which requires more power support. While AI architectures continue to improve power efficiency, they can't keep up with the power demand from the growth in compute.
As transistor densities increase, these problems become more problematic. What used to fit in a planar SoC has to be spread across multiple chiplets because static random access memory (SRAM) can't keep up with the latest process nodes, and specialized processing components are increasingly used. While the chiplet combination has resulted in a significant increase in performance, it has also increased power consumption. Nowadays, the power of some system-on-chip is already as high as several hundred watts, and the chips in the chiplet system are densely stacked, and the power consumption is greatly increased. In addition, the supply voltage is getting lower and lower, which makes the absolute deviation of the voltage smaller and smaller, and it is difficult to install stable components such as capacitors in small chip systems, so uniform power supply simulation or verification is also complicated because there is no uniform standard for the interface between the chip and the package.
To accommodate more computing elements, chipmakers are stacking more and more memory and logic elements vertically. Interposers are used in many designs today, but this may change in the future to improve power efficiency. In 2.xD systems, high-density chip-to-chip interfaces such as UCIe can increase the number of package layers or require an interposer, which can lead to poor capacitance and voltage regulation on the ball side of the package or on the printed circuit board (PCB), so these components must be integrated into the interposer or package substrate. However, the larger size of these packages and the stiffer the substrate, which often means increasing the thickness of the core layer, which makes it more difficult to achieve sufficient power supply through the package because the density of plated through-hole (PTH) decreases and the inductance increases. 3D-ICs solve some of the problems with thinner substrates and metal layers, but higher currents and more voltage domains per unit can lead to power integrity issues and parasitic effects.
Figure: The power challenge posed by chiplets
In a heterogeneous mix of chiplets, power-related issues interact in a unique way. The greater the number of chips, the thinner the material and dielectric, and the heavier the computational task, the greater the impact on the power supply. Powering where power is needed becomes harder, poor cooling accelerates aging, blocking data transfer paths, and thermal gradients for specific workloads can impact performance and power consumption in unexpected ways. Electromigration, for example, is essentially not much different from what happens on a single chip, but it is more problematic in chiplet combinations. Because the power supply network is interrelated, not point-to-point connection like the signal line, but the power grid on the entire chip is connected to each other, and the power grid of each chiplet and interposer layer has many connection points, and a certain part cannot be analyzed separately and then simply added, and the entire grid of all chips, interposers and packages must be co-simulated to accurately calculate the voltage drop, but this is time-consuming and takes up memory, so a better way is to use a reduced-order model.
There are commercial tools that can analyze a chip's power grid to generate a chip power model (CPM), but in a chiplet system, designing a power delivery network is much more complex than a single SoC chip. On a single chip, the main problem is that the routing density increases as the process nodes shrink; In chiplet designs, bumps and through-silicon vias to connect and align are very cumbersome. The number, size, and spacing of bumps affect not only the power connection, but also the maximum temperature of the chip. Moreover, the more computational elements there are in the design, the more difficult it is to analyze manually, which is where artificial intelligence or machine learning comes in.
In chiplet design, early planning becomes crucial. In the past, when designing SoC chips, there was a fixed package, which was relatively simple to design; Chiplet systems can be packaged in a variety of ways, either through an interposer or a true 3D-IC stack, so it's important to plan ahead from a system-wide perspective, build early models, and consider trade-offs such as which technology or multi-chip packaging will meet the design requirements.
Modeling the entire chiplet is also challenging, as there are so many and complex elements to model that hierarchical modeling is necessary. Look at the voltage at the board level, and then subdivide it into individual chiplets for detailed modeling and analysis. There used to be a well-established approach to power supply design, but it is less applicable to the complex design of chiplets. There are clear standards and verification methods for signal integrity, but there is no uniform standard for power integrity. In addition to high-frequency power supply noise, there is also low-frequency power supply noise, which is an emerging problem in distributed chiplet systems, and needs to be dealt with by a separate low-frequency model.
The power integrity of chiplets faces many challenges, such as IR voltage drop, and the connection between chips requires a lot of signal bumps, which occupies power bumps and wiring resources, making it difficult to reduce the voltage drop, and the faster the data transmission speed between chips, the more serious the problem; The power distribution network (PDN) is complex, with chiplets sharing power rails introducing additional noise coupling and potentially hot spots, and PDNs include multiple parts on-chip, inside the interposer/bridge, and package substrate, all of which need to be accurately modeled. Discontinuities in the power supply and ground plane increase impedance, and parasitic inductance and capacitance from interconnects can affect signal quality, making it difficult to obtain a correct model of these components; The placement of the decoupling capacitor is also troublesome, the capacitor on the board is too far away from the active circuit and does not work, but the space at the chip interface is limited, and the distribution of the decoupling capacitor is limited; Different chiplets have different power states, which can lead to uneven power consumption, and the transient currents generated by high-speed switching components need to be handled carefully. Chiplet designs have high power densities, which can generate hot spots that affect power integrity, and thermal modeling is complex; Differences in the manufacturing process, such as changes in bump height, bond quality, interposer resistance, and process differences between chiplets produced by different foundries, can affect power integrity.
To address these issues, architects and designers can start with a number of aspects when designing chiplets. In the early stage of design, special attention should be paid to the structure and characteristics of PDN, and advanced simulation tools should be used for analysis to optimize the model in advance. It is necessary to have a good decoupling strategy and reasonably distribute the decoupling capacitors on the chip and at the package level; Avoid the sharing of power rails between high-noise and low-noise chiplets, and divide independent power domains; A low-dropout regulator is used on the chip to regulate the power supply and filter out noise; Dynamic power management using Adaptive Voltage Scaling (AVS) or Dynamic Voltage and Frequency Scaling (DVFS) technology; Thermal-aware design takes heat dissipation and power integrity into account to optimize chiplet layout; Considering various differences in the manufacturing process, we work closely with packaging and testing factories and foundries; There is extensive verification after manufacturing to ensure power integrity.
In conclusion, power-related issues are much more difficult in chiplet design than planar SoC chip design, and must be carefully planned at the beginning of the design and a more systematic design approach must be adopted to ensure reliable chiplet system performance.
