In the development of semiconductor technology, CMOS (complementary metal-oxide semiconductor) technology has been the core driving force for the industry to move forward. However, as the physical limit approaches, traditional CMOS technology is facing unprecedented challenges. The CMOS 2.0 concept proposed by Julien Ryckaert, vice president of logic technology at imec, heralds a paradigm shift in the semiconductor industry.
Achievements and limitations of CMOS technology
CMOS technology has achieved significant performance improvements and cost reductions by continuously reducing transistor sizes. According to the International Semiconductor Technology Roadmap (ITRS), transistor density has increased by a factor of about 1,600 from the 0.8-micron process in the 1990s to the 5-nanometer process in the 2020s. But with the diminishing benefits of size scaling, traditional CMOS technologies are facing reduced PPAC (performance, power, area, and cost) returns.
CMOS 2.0: Heterogeneous Integration and System Optimization
CMOS 2.0 proposes a new approach to SoC design, which divides the SoC into different functional layers through System Technology Co-Optimization (STCO) and selects the most appropriate technology option for each layer. This approach allows each tier to be optimized for its specific functional constraints, resulting in higher performance and lower costs. For example, imec showcased Cu/SiCN wafer-to-wafer bonding technology with interconnect pitches as low as 400 nm, providing robust connectivity for 3D integration.
Figure: CMOS 2.0 in the semiconductor technology revolution
3D Integration Technology: Connectivity and Flexibility
The implementation of CMOS 2.0 relies on advanced 3D integration technologies that can reconnect different functional layers as if they were on the same substrate. Developments in 3D integration technologies, such as submicron interconnect pitch connections through hybrid wafer-to-wafer bonding, provide greater connectivity performance and flexibility for the heterogeneous layers of SoCs.
Logic innovation: high-drive logic layer and high-density logic layer
CMOS 2.0 also proposes an innovative division of the logic part of the SoC. In this approach, the logic part is divided into a high-driving logic layer and a high-density logic layer, each optimized for different performance needs. This division allows for the introduction of new materials and technologies, such as 2D materials and CFET architectures, while maintaining Moore's Law.
Conclusion: Future prospects and challenges of CMOS 2.0
CMOS 2.0 represents a paradigm shift in the semiconductor industry, providing not only greater flexibility and optimization options for SoC design, but also a broader technology platform for a variety of computing applications. However, achieving CMOS 2.0 requires close collaboration across the semiconductor ecosystem, including innovation in design practices, system architecture, EDA tools, and manufacturing processes. Gartner predicts that by 2025, more than 50% of SoCs will use heterogeneous integration technologies, indicating that CMOS 2.0 is promising, but also challenging.
Note: What is a paradigm shift?
The term "paradigm shift" was first coined by the historian and philosopher of science Thomas Kuhn in his 1962 book, The Structure of Scientific Revolutions. It refers to a fundamental change that occurs in the field of scientific theory, methodology, or technical practice that changes the basic assumptions, experimental methods, and theoretical frameworks within a field. Paradigm shifts are often accompanied by the challenge of old models and the acceptance of new ideas, and it can lead to the restructuring of entire industries or social structures with far-reaching consequences.
