It is reported that the JEDEC Solid State Technology Association is nearing completion of the highly anticipated HBM4 standard for next-generation high-bandwidth memory (HBM) DRAM. The HBM4 standard is an evolution of the HBM3 standard and aims to further increase data processing rates while maintaining essential features such as higher bandwidth, lower power consumption, and increased capacity per chip or stack. These advancements are critical for applications that need to efficiently handle large data sets and complex calculations, including generative artificial intelligence (AI), high-performance computing, high-end graphics, and servers.
HBM4, the latest version of HBM's memory series, offers significant advancements in several areas. First, the number of stacked channels has been doubled, which means that HBM4 is able to provide higher bandwidth and data processing power at the same physical size. This feature is critical for handling large-scale datasets and complex computing tasks, especially in areas such as generative AI, high-performance computing (HPC), and high-end graphics and servers.
In addition to the increase in the number of channels, the physical size of HBM4 has also increased, resulting in an increase in storage capacity. In addition, JEDEC has tentatively agreed to a maximum speed of 6.4 Gbps for HBM4 and is exploring the possibility of achieving higher frequencies. This increase in speed will greatly speed up the data transfer speed, further improve the performance of the system, and meet the increasing demand for data processing.
The development of the HBM4 standard is not only a technological breakthrough, but also will have a profound impact on the entire industry.
First, it will drive continued innovation in memory technology. In order to meet the high performance requirements of HBM4, manufacturers will have to invest more resources in developing more advanced packaging technologies, chip designs, and thermal solutions. These efforts will drive overall advancements in memory technology, bringing more efficient and reliable solutions to the market.
Figure: JEDEC is about to finalize the HBM4 specification (Source: Cnbeta).
Second, the launch of HBM4 will meet the urgent needs of high-end applications for memory bandwidth and data processing capabilities. In areas such as generative AI and HPC, the explosive growth of data has posed unprecedented challenges to memory technology. With its excellent performance indicators, HBM4 will become an indispensable key component in these fields and drive the rapid development of related applications.
In addition, the implementation of the HBM4 standard will also promote the upgrading and reconstruction of the entire industrial chain. Manufacturers will need to adapt their production processes and product designs to new standards. This will promote the collaboration of upstream and downstream enterprises in the industry chain to jointly promote the development and progress of memory technology.
It is predicted that HBM4 with 12- and 16-layer DRAM designs is expected to reach mass production in 2026. This marks that HBM4 technology will gradually move towards the stage of commercial application, bringing more efficient and reliable memory solutions to the market. With the continuous maturity of technology and the gradual reduction of costs, HBM4 is expected to be applied in a wider range of fields, injecting new impetus into the development of the industry.
However, the design and production of HBM4 also faced a number of challenges. How to ensure the signal integrity under high-speed data transmission, how to optimize the package structure to improve heat dissipation performance, etc., need to be gradually solved in the subsequent R&D and production process. In addition, with the continuous advancement of technology and the continuous expansion of application scenarios, the HBM4 standard may also need to be continuously adjusted and improved to meet new requirements.
