As a key link in chip manufacturing, semiconductor interconnect technology is on the eve of major changes. Interconnects Approach Tipping Point, published by semiengineering, focuses on the evolution of interconnect technology in semiconductor manufacturing, providing an in-depth look at the challenges of interconnect technology and upcoming material and process innovations as chip manufacturing approaches the 10-angstrom node. The author of this article is an editor with rich experience in semiconductors, whether it is an industry practitioner or a reader interested in the development of semiconductor technology, you can get cutting-edge information about new interconnection materials such as ruthenium and molybdenum, as well as related innovative processes, and have an in-depth understanding of the future trend of the semiconductor interconnection field. The following editor of China Exportsemi will interpret the core content of the article:
In semiconductor manufacturing, interconnect technology is on the verge of a major change. As the chip manufacturing process moves towards the 10-angstrom node, new architectures, tools, and materials are emerging that will dramatically change the way fabs build interconnects. Among them, the Damascus process occupies an important position in the current semiconductor interconnect manufacturing and is closely related to future changes.
The Damascus process, which is divided into single Damascus process and double Damascus process, is a technology widely used in the formation of metal interconnect layers in semiconductor manufacturing. In the case of the double Damascus process, for example, in the manufacture of metal interconnects, grooves and through-holes are etched into the dielectric layer (usually a dielectric insulator) and then filled with metal (such as copper) through a specific process. In the filling process, the vias are generally filled first, and then the trenches are filled to form a metal interconnect line to realize the electrical connection between the different devices in the chip.
At present, in copper interconnection, the Damascus process is widely used. But as the chip process continues to shrink and move to more advanced nodes, the process has also exposed some problems. For example, at tiny line widths and pitches, copper interconnects require the addition of barriers, liners, and caps to prevent copper from spreading to adjacent areas and provide good conditions for plating filling. However, these extra layers not only occupy valuable conductor space, but also have a higher resistivity of their own than copper, resulting in an increase in overall resistance. For example, in a 10 nm wide line, after depositing the TaN barrier, cobalt liner and cobalt cap, the actual effective copper width may be only 4 nm - 5 nm. In addition, with interconnect pitches approaching 20nm, it is becoming increasingly difficult for deposition tools to guarantee that the filling is defect-free or void-free when filling tiny gaps through electroplating in the traditional Damascus process. For example, when the interconnect pitch becomes smaller, thinning the cobalt liner can lead to poor copper wettability, which in turn can lead to reliability issues.
Figure: Roadmap of ruthenium and air-gapped. (Source: imec)
As the industry moves towards more advanced processes, such as the 10-angstrom node, process adjustments may need to be made to address these challenges. One trend is to move from processes based on the Damascus process to a subtractive deposition-etching process. Taking ruthenium interconnects as an example, although the existing Damascus process can be used for ruthenium interconnects, the subtractive method has more advantages, as it can reduce the wobble and distortion of lines under tight dimensions, and achieve higher aspect ratio line manufacturing, which is more compatible with future CFET structures. However, switching to a new process was not an easy task, and a number of technical challenges needed to be addressed to ensure that the new process met requirements such as reliability for mass production.
At present, with the development of advanced logic devices to the next generation of nanosheet structures, their interconnects are facing severe challenges. At the 1nm (10 angstrom) node, the interconnect stack already consumes one-third of the device's power and accounts for 75% of the chip's RC latency, despite the 20nm metal wire pitch and larger line widths. To solve these problems, the industry urgently needs better quality conductors. While copper-based solutions are still widely used in fabs, the transition from copper to alternative metals is already underway.
Among the many alternatives, ruthenium (Ru) and molybdenum (Mo) are in the spotlight. Ruthenium may be used as early as the 14-angstrom node to replace the copper interconnect of the lowest and tightest connecting layer. Many leading logic fabs, such as TSMC, Intel, IBM Research Center, and Samsung, are working on ruthenium-based interconnect integration solutions. Ruthenium does not need a barrier layer, can be directly etched, is not easy to oxidize, and the average free path of electrons is short, which can reduce the influence of scattering on resistance under short line width. In addition, the use of subtractive etching to replace the existing Damascus process can reduce the wobble and twist of the lines under tight dimensions, enabling higher aspect ratio line fabrication and better adaptation to future CFET structures. However, integrating an air gap into a device reduces capacitance but reduces mechanical stability, so air gaps may be used alternately and in small quantities.
Molybdenum is expected to be the successor to tungsten interconnects for DRAM and 3D NAND. Nearly all major chipmakers are evaluating the use of molybdenum in NAND, DRAM, and logic applications at some stage. In addition to being compatible with existing Damascus processes and eliminating the need for a barrier layer, molybdenum is also a major advantage of its low cost. By depositing molybdenum at 400°C by ion beam deposition, a lower resistivity than tungsten can be obtained and the grain structure can be optimized.
Chipmakers are still making improvements to existing copper and tungsten-based interconnect processes until materials are completely converted. For example, in the double Damascus process, performance is improved by employing a low-resistance via process, atomic layer deposition of a thinner TaN diffusion barrier, the use of alternative gaskets such as ruthenium-cobalt, and the elimination of the barrier layer at the bottom of the via. Samsung has reported optimizing the ruthenium-cobalt liner to improve the copper gap filling at the 3nm node.
In addition to the material revolution, there is also a significant change in the way interconnect is manufactured. Backside Power Delivery (BPD) technology transfers power transfer to the back of the wafer, allowing the interconnect layer above the transistor to transmit the signal only. This change could relax the metal pitch requirements on the front of the wafer and potentially delay the introduction of ruthenium at certain device nodes.
But these changes didn't happen overnight. The shift from a Damascus process-based process to a subtractive deposition-etching process, as well as a material transition from copper to ruthenium, is a huge game-changer for logic manufacturers' interconnect processes. The process of achieving molybdenum interconnects is also evolving at a rapid pace, with the aim of finding the best combination of materials and equipment. In the semiconductor industry, material and architecture changes are only driven when existing processes do not meet performance requirements. Given the huge investment in tools, materials and process formulations for copper double Damascus and tungsten metallization, any metal substitution will be done gradually.
Original：Interconnects Approach Tipping Point
