Synopsys introduces the industry's first Universal Chiplet Interconnect Express (UCIe) IP solution running at 40 Gbps, a technological advancement that will dramatically advance high-performance multi-chip system designs. UCIe is an open, industry-standard interconnect that provides a high-bandwidth and low-latency solution for chip-to-chip connectivity in multi-chip designs. This new IP solution from Synopsys includes controller, physical layer (PHY) and verification IP designed to support chip-to-chip connectivity in high-performance artificial intelligence data center chips.
This technology is particularly suitable for applications that require large amounts of data processing and low latency, such as AI training, high-performance server chips, advanced driver assistance system (ADAS) chips, and more. Synopsys' 40G UCIe IP solutions are built on a proven architecture that has achieved interoperability and silicon validation across multiple advanced foundries and processes. It supports both organic substrates and high-density advanced packaging technologies, giving customers the flexibility to explore the packaging options that best suit their needs.
Advanced features of the Synopsys 40G UCIe IP solution include:
Simplified solution simplifies IP integration: The single-reference clock feature simplifies the clock architecture and optimizes power consumption. For ease of use and integration, the IP accelerates inter-chip link initialization without the need to load firmware.
Silicon Health Monitoring Improves Reliability in Multi-Chip Packages: To ensure reliability at the chip, chip-to-chip, and multi-chip package level, Synopsys 40G UCIe IP provides test and silicon lifecycle management (SLM) capabilities. Monitoring, testing, and repairing IP and integrated signal integrity monitors enable diagnostics and analysis of multi-chip packages from design to the field.
Actionable Ecosystem Interoperability: For on-chip interconnect needs for the latest CPUs and GPUs, Synopsys 40G UCIe IP supports the most popular on-chip interconnect fabrics, including AXI, CHI chip-to-chip, streaming, PCI Express, and CXL. For successful interoperability, the IP is UCIe 1.1 and 2.0 compliant, and Synopsys is committed to developing and promoting these standards as an active member of the UCIe Alliance.
Figure: Synopsys Launches 40Gbps IP Solution (Source: Synopsys)
Pre-Validated Design Reference Flow: The combination of Synopsys UCIe IP and Synopsys 3DIC Compiler is a unified discovery-to-signoff platform for Synopsys' pre-validated design reference flow, which includes all required design materials such as auto-routing flow, interposer studies, and signal integrity analysis.
Broad IP solutions for multi-chip designs: In addition to UCIe IP and high-speed SerDes, Synopsys offers HBM3 and 3DIO IP for high-capacity memory and 3D packaging.
In addition, Synopsys' 40G UCIe IP provides higher bandwidth than the UCIe specification without compromising energy efficiency and silicon area. It integrates signal integrity monitors and testability features to improve the reliability of multi-chip system packages and allow for on-site monitoring throughout the silicon lifecycle. Synopsys also offers a pre-validated design reference flow, which integrates with the Synopsys 3DIC Compiler to provide customers with the design materials and documentation needed for automated routing processes, interposer studies, and signal integrity analysis.
The evolution of this technology is a testament to Synopsys' leadership in the evolution of UCIe, driving not only semiconductor innovation, but also providing customers with comprehensive, scalable, multi-chip solutions from early architecture exploration to manufacturing. As the demand for data-intensive applications continues to grow, Synopsys' 40Gbps UCIe IP will enable customers to enable efficient, high-bandwidth chip-to-chip connectivity to meet the needs of the world's fastest AI data centers.
