What are the common features of the increasingly important advanced semiconductor technologies such as CowoS, Crystal Back Power Supply, HBM, 3DNAND, etc.? According to Asianometry, a blogger on YouTube, the common denominator of emerging semiconductor technologies is that they all rely on some form of wafer bonding. Asianometry has a large fan base on YouTube, and he focuses on analyzing the history, economy, and development of the semiconductor industry in Asia. In his video, Why Wafer Bonding is the Future of Semiconductors, he details the seemingly simple but important technology of wafer bonding. In this article, we will learn about the wafer bonding technology introduced by blogger Asianometry in the video.
Wafer bonding can be divided into several types:
Silicon Wafer Bonding Silicon wafer bonding refers to the union of two clean, highly polished silicon wafers that are pressed together at vacuum room temperature and they will stick. This is supported by capillary forces, hydrogen bonds, and so on, but the most important of them is the Van der Waals force. The van der Waals force refers to the weak point of attraction between uncharged atoms or molecules, and the strength of the force depends on the distance of the wafer, surface roughness, etc., so the relative effect is weak. To prevent accidental wafer stripping, a high-temperature annealing step is added to almost all wafer bonding technologies. In addition, simply gluing two wafers together can also be called wafer bonding, but this method is not the way most people think of wafer bonding, and it does not contain too high technical content.
Cold Welding Cold Welding bonding has long been known as the method of pressing two pieces of metal together in a vacuum, and the two pieces of metal will fuse. Cold soldering has been used to unite objects since 1700, when it was proved that it takes the same force to separate two pieces of lead as it does to separate a ball of lead. This phenomenon is even more famous in European optical workshops, where the staff of the optical workshop found that the polished glass surfaces would merge when pressed together, which was at first considered a nuisance, but later it was discovered that when the glass parts were cold-welded together, the boundary between the two could not be seen because there was no reflection. Today, cold welding technology still deserves our attention.
Anodizing Bonding So how did cold soldering technology enter the semiconductor industry? In 1969, Wallis and Pomerantz published the results of bonding silicon wafers to nanoglass, and found that only relatively low heat (500 degrees Celsius) and an electric field were used, without the use of an intermediate layer. This technique is known as anodic bonding or electrostatic bonding. This technique is most commonly used to link silicon and borosilicate glass wafers, placing them directly on a hot plate and applying a high DC voltage. However, the anode bonding market is very small, and there are not many market applications except for the MEMS or microfluidics industries, which are expected to be about $20 million per year.
Silicon-on-insulator (SOI) wafer bonding first made its mark in the industry in the 1980s, when a new technology called insulated silicon, or SOI, was being developed. SOI is the placement of a thin silicon wafer loaded with a transistor on an insulator, usually silicon dioxide. Since the early 1960s, SOI has been being studied to increase transistor density. Most silicon wafers are about 500 microns thick, and the transistor layer accounts for only about one micron of them. Therefore, phenomena such as parasitic capacitance, short-channel effects, etc., that cause leakage, are caused by the interaction between the thin crystal layer and the underlying substrate. Thinning the wafer that carries the component and then placing the insulation layer under the transistor can reduce the short-channel effect and thus save power consumption.
Figure: Silicon overlying insulation
Direct Wafer Bonding Direct wafer bonding, also known as fusion bonding, is the most common type of bonding in which two wafers are pressed together without an intermediate layer of material, and then annealed to strengthen the bond between the wafers. Depending on the nature of the wafer surface, direct bonding is divided into three subcategories, one is the hydrophilic surface, which has an oxide layer and an aqueous layer before bonding. The second is the hydrophobic surface, which removes hydrogen and silicon through hydrofluoric acid. Finally, there is an ultra-clean silicon surface, which is bonded under ultra-vacuum conditions. Today, direct bonding is used to bond very thin layers, such as an insulating layer covered with silicon. These layers are often not self-supporting, so they are bonded directly to a mechanical substrate, maintaining stability. A similar situation can occur on the crystal-back power supply network. Die back power is the network of copper wires that provide power to the transistor is moved underneath the transistor, while direct bonding is the bonding of the transistor element wafer to the carrier wafer to facilitate mechanical stability during the subsequent thinning step.
Factors influencing bond yield
Manufacturers want good wafer bonding yields, so how do you ensure good bonding? There are several factors: First, before bonding, the wafer must be made flat and clean, if it is not flat enough, there will be areas on the wafer that cannot be bonded and bubbles will be generated.
Second, the cleanliness of the surface is also important, if the cleanliness is not enough, small particles sandwiched between two wafers can lead to serious defects, creating voids and bubbles that weaken the adhesion. Even particles as small as 1 micron wide can produce bubbles several millimeters wide, so it is essential to wrap up the wafer surface as much as possible and bond in a clean room.
3. Alignment. If there is no alignment, the two wafers will not be connected together.
A few years ago, Intel redefined Moore's Law from computing ICs, and the number of transistors was changed to count the number of transistors in a package, which is an increasingly important sign in the packaging industry. Scaling on the IC can still continue to shrink, but the scaling speed and cost are not the same as before. In the future, it will be more difficult to effectively avoid short-channel effects and leaks, so improving advanced packaging technology will benefit wafer bonding and other related technologies. Looking forward to seeing more breakthroughs in the coming years.
